Abstract
The rapid proliferation of safety-critical and cyber-physical systems in domains such as automotive electronics, unmanned aerial vehicles, industrial automation, and intelligent energy infrastructures has intensified the demand for computing platforms that combine high performance with stringent fault tolerance and functional safety guarantees. Contemporary systems increasingly rely on multicore and heterogeneous processor architectures, which, while offering superior computational capabilities, introduce complex reliability challenges stemming from transient faults, permanent hardware failures, electromagnetic interference, and design-induced vulnerabilities. Lockstep-based execution paradigms have emerged as a foundational architectural strategy to address these challenges by enabling timely error detection, fault isolation, and deterministic recovery. This article presents a comprehensive and theoretically grounded investigation of lockstep and lockstep-inspired fault-tolerant architectures, drawing exclusively on the provided body of scholarly and industrial references. The discussion spans classical redundancy principles, including dual-core and triple modular redundancy, as well as modern evolutions such as light lockstep, heterogeneous Arm–RISC-V lockstep systems, dynamically coupled cores, and flexible vector lockstep execution in ultra-low-power clusters. Beyond architectural mechanisms, the article situates lockstep computing within broader system-level considerations, including power supply safety design, compliance with functional safety standards, fault injection methodologies, and emerging application contexts such as autonomous vehicles, UAVs, edge intelligence, and secure energy trading. Through extensive theoretical elaboration, the article identifies critical trade-offs between performance, power efficiency, detection latency, and design complexity, while highlighting persistent gaps in scalability, adaptability, and cross-layer integration. The findings underscore that lockstep architectures, when combined with system-aware design principles and rigorous validation strategies, constitute a central pillar for dependable computing in next-generation safety-critical systems.