High-performance digital systems require efficient multipliers that can provide low area, low power, and high-speed operation. Traditional multiplier designs often face trade-offs between area, speed, and power consumption, impacting overall system efficiency. This study presents a novel compact multiplier architecture leveraging multiplexer-based full adders to optimize both area and speed. By replacing conventional adders with multiplexer-based full adders, the design achieves significant area reduction without compromising computational accuracy or performance. Through simulation and analysis, the proposed design demonstrates improved delay and reduced hardware complexity compared to traditional architectures. The results indicate that the multiplexer-based full adder is an effective approach for achieving compact, high-speed multipliers suited for advanced digital systems, including signal processing and low-power applications. This work offers valuable insights into optimizing multiplier circuits and highlights the potential of multiplexer-based components in VLSI design.

High-speed multiplier, Low-area multiplier, Multiplexer-based full adder

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